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fast automotive sensor signal conditioner zsc31150 datasheet ? 2016 integrated device technology, inc . 1 december 6, 2016 brief description the zsc31150 is a cmos integrated circuit for highly accurate amplification and sensor - specific correction of bridge sensor signals. digital compensation of sensor offset, sensitivity, temperature drift, and non - linearity is accomplished via a n internal 16 - bit risc microcontroller running a correction algorithm, with calibration coefficients stored in an eeprom. the zsc31150 is adjustable to nearly all bridge sensor types. measured values are provided at the analog voltage output or at th e digital zacwire ? and i 2 c interface. the digital interface can be used for a simple pc - c ontrolled calibration pro cedure in order to program a set of calibration coefficients into an on - chip eeprom. a specific sensor and a zsc31150 can be mated digitally: fast, precise, and without the cost overhead associated with trimming by external devices or a laser. features ? digital compensation of sensor offset, sensitivity, temperature drift, and non - linearity ? adjustable to nearly all bridge sensor types ? a nalog gain of up to 420 ? output options: ratiometric analog voltage output (5 % to 95% maximum, 12.4 - bit resolution) or zacwire ? (digital one - wire - interface) ? temperature compensation: internal or external diode, bridge resistance, thermistor ? sensor biasing by voltage or constant current ? sample rate : up to 7.8 khz ? h igh voltage protection up to 33 v ? supply current : max. 5.5ma ? reverse polarity and short - circuit protection ? wide operation temperature depending on part number: up to - 40 c to +150c ? traceability by user - defi ned eeprom entries ? s afety and diagnostic functions benefits ? no external trimming components required ? only a few external protection devices needed ? pc - controlled configuration and single pass calibration via i 2 c or zacwire ? interface: s imple, cost efficien t, quick, and precise ? end - of - l ine calibration via i 2 c or zacwire ? interface ? high accuracy (0.25 % fso at - 25 to 85c; 0.5% fso at - 40 c to 125c) ? excellent emc/esd robustness and aec - q100 qualification available support ? evaluation kit s ? application notes ? ma ss c alibration system physical characteristics ? supply voltage : 4.5v to 5.5 v ? operation temperature: - 40c to 125c ( - 40c to +150c extended temperature range ) ? available as 14 - dfn (5 ? 4 mm ; wettable flank s ), ssop14, and die zsc31150 a pplication circuit 2 1 3 4 6 5 7 1 4 1 3 1 2 1 1 1 0 8 s e r i a l i n t e r f a c e s e n s o r b r i d g e s d a s c l o u t / o w i g n d v s u p p c 3 4 7 n f + 4 . 5 v t o + 5 . 5 v z s c 3 1 1 5 0 v d d a v s s a s d a s c l n . c . v d d v d d e i r t e m p v b r _ t v b p v b r _ b v b n a o u t v s s e 9 c 2 1 0 0 n f c 1 1 0 0 n f t e m p e r a t u r e s e n s o r c 5 c 4
zsc31150 datasheet ? 2016 integrated device technology, inc . 2 december 6, 2016 zsc31150 block diagram ordering informatio n sales code description package zsc31150ge zsc31150 die C temperature range: - 40c to +150c unsawn on wafer: add b to sales code sawn on wafer frame: add c waffle pack: add d zsc31150geg2 - r zsc31150 14 - dfn (5 ? 4 mm ; wettable flank s ) C temperature range: - 40c to 150c tape and reel zsc31150gag2 - r zsc31150 14 - dfn (5 ? 4 mm; wettable flank s ) C temperature range: - 40 c to 125 c tape and reel zsc31150gab zsc31150 die C temp erature range: - 40c to +125c unsawn on wafer zsc31150gac zsc31150 die C temperature range: - 40c to +125c sawn on wafer frame zsc31150geg1 zsc31150 14 - ssop C temperature range: - 40c to +150c tube: add - t to sales code tape & reel: add - r zsc31 150glg1 zsc31150 14 - ssop C temperature range: - 40c to +150c (long life: 5000h @150c) ZSC31150GAG1 zsc31150 14 - ssop C temperature range: - 40c to +125c zsc31150kitv1p2 zsc31150 ssc evaluation kit v1.2: three interconnecting boards, five zsc31150 ss op14 samples, usb cable (software can be downloaded from product page at www.idt.com/zsc31150) zsc31150mcsv1p1 modular mass calibration system (msc) v1.1 for zsc31150: mcs boards, cable, connectors (software c an be downloaded from product page) corporate headquarters 6024 silver creek valley road san jose, ca 95138 www.idt.com sales 1 - 800 - 345 - 7015 or 408 - 284 - 8200 fax: 408 - 284 - 2775 www.idt.com/go/sales tech support www.idt.com/go/support disclaimer integrated device technology, inc. (idt) reserves the right to modify the products and/or specifications described herein at any time, without notice, at idt's sole discretion. performance specifications and operating parameters of the described products are determined in an independent state and are not guarante ed to perform the same way when installed in customer products. the inf ormation contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt's products for any particular purpose, an implied warranty of merchantability, or non - in fringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications in volving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the united states and other countries. other tradema rks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . all contents of this document are copyright of integrated device technology, inc. all rights reserved. p g a t s a d c c m c r o m r a m e e p r o m d a c b a m p z a c w i r e ? i 2 c m u x a n a l o g b l o c k d i g i t a l b l o c k z s c 3 1 1 5 0 d i g i t a l d a t a i / o a n a l o g o u t
zsc31150 datasheet ? 2016 integrated device technology, inc . 3 december 6, 2016 contents 1. electrical characteristics ................................ ................................ ................................ ................................ ................................ .............. 5 1.1 absolute maximum ratings ................................ ................................ ................................ ................................ ................................ . 5 1.2 operating conditions ................................ ................................ ................................ ................................ ................................ ........... 5 1.3 electrical parameters ................................ ................................ ................................ ................................ ................................ .......... 6 1.3.1 supply current and system operation conditions ................................ ................................ ................................ ............... 6 1.3.2 an alog front - end (afe) characteristics ................................ ................................ ................................ .............................. 6 1.3.3 temperature measurement [b] ................................ ................................ ................................ ................................ ............... 6 1.3.4 analog - to - digital conversion (adc) ................................ ................................ ................................ ................................ ..... 7 1.3.5 sensor connection check ................................ ................................ ................................ ................................ .................... 7 1.3.6 digital - to - analog conversion (dac) and analog output (aout pin) ................................ ................................ .................. 7 1.3.7 system response ................................ ................................ ................................ ................................ ................................ 8 1.4 interface characteristics and eeprom ................................ ................................ ................................ ................................ .............. 8 1.4.1 i 2 c interface [a] ................................ ................................ ................................ ................................ ................................ ...... 8 1.4.2 zacwire? one wire interface (owi) ................................ ................................ ................................ ................................ .. 9 1.4.3 eeprom ................................ ................................ ................................ ................................ ................................ .............. 9 2. circuit d escription ................................ ................................ ................................ ................................ ................................ ...................... 10 2.1 signal flow ................................ ................................ ................................ ................................ ................................ ........................ 10 2.2 application modes ................................ ................................ ................................ ................................ ................................ ............. 10 2.3 an alog front end (afe) ................................ ................................ ................................ ................................ ................................ .... 11 2.3.1 programmable gain amplifier (pga) ................................ ................................ ................................ ................................ . 11 2.3.2 offset compensation ................................ ................................ ................................ ................................ .......................... 11 2.3.3 measurement cycle ................................ ................................ ................................ ................................ ............................ 12 2.3.4 analog - to - digital converter ................................ ................................ ................................ ................................ ................ 13 2.4 temperature measurement ................................ ................................ ................................ ................................ ............................... 15 2.5 system control and conditioning calculation ................................ ................................ ................................ ................................ ... 15 2.5.1 operation modes ................................ ................................ ................................ ................................ ................................ 15 2.5.2 start up phase ................................ ................................ ................................ ................................ ................................ ... 15 2.5.3 conditioning calculation ................................ ................................ ................................ ................................ ..................... 16 2.6 analog output aout ................................ ................................ ................................ ................................ ................................ ......... 16 2.7 serial digital interface ................................ ................................ ................................ ................................ ................................ ....... 16 2.8 failsafe features, watchdog and error detection ................................ ................................ ................................ ............................. 17 2.9 high v oltage, reverse polarity, and short circuit protection ................................ ................................ ................................ ............ 17 3. application circuit examples ................................ ................................ ................................ ................................ ................................ ...... 18 4. pin configuration, latch - up and esd protection ................................ ................................ ................................ ................................ ....... 20 4.1 pin configuration and latch - up conditions ................................ ................................ ................................ ................................ ....... 20 4.2 esd protection ................................ ................................ ................................ ................................ ................................ .................. 20 5. package ................................ ................................ ................................ ................................ ................................ ................................ ...... 21 5.1 ssop14 package ................................ ................................ ................................ ................................ ................................ .............. 21 5.2 14 - dfnpackage ................................ ................................ ................................ ................................ ................................ ................ 21
zsc31150 datasheet ? 2016 integrated device technology, inc . 4 december 6, 2016 6. quality and reliability ................................ ................................ ................................ ................................ ................................ ................. 22 7. customization ................................ ................................ ................................ ................................ ................................ ............................. 22 8. ordering information ................................ ................................ ................................ ................................ ................................ ................... 23 9. related documents and tools ................................ ................................ ................................ ................................ ................................ ... 23 10. glossary ................................ ................................ ................................ ................................ ................................ ................................ ..... 24 11. document revision history ................................ ................................ ................................ ................................ ................................ ........ 25 list of figures figure 2.1 block diagram of the zsc31150 ................................ ................................ ................................ ................................ ....................... 10 figure 2.2 measurement cycle ................................ ................................ ................................ ................................ ................................ ........... 13 figure 3.1 bridge in voltage mode, external diode temperature sensor ................................ ................................ ................................ .......... 18 figure 3.2 bridge in voltage mode, external thermistor ................................ ................................ ................................ ................................ .... 19 figure 3.3 bridge in current mode, temperature measurement via bridge tc ................................ ................................ ................................ . 19 figure 5.1 ssop14 pin diagram ................................ ................................ ................................ ................................ ................................ ........ 21 figure 5.2 outline drawing for 14 - dfn package with wettable flanks ................................ ................................ ................................ ............. 22 list of tables table 1.1 absolute maximum ratings ................................ ................................ ................................ ................................ ................................ . 5 table 1.2 operating conditions ................................ ................................ ................................ ................................ ................................ ........... 5 table 1.3 electrical parameters ................................ ................................ ................................ ................................ ................................ .......... 6 table 1.4 interfac e and eeprom characteristics ................................ ................................ ................................ ................................ .............. 8 table 2.1 adjustable gains, resulting sensor signal spans, and common mode ranges ................................ ................................ ............. 11 table 2.2 an alog zero point shift ranges (xzc) ................................ ................................ ................................ ................................ .............. 12 table 2.3 analog output resolution versus sample rate ................................ ................................ ................................ ................................ 14 table 3.1 application circuit par ameters ................................ ................................ ................................ ................................ .......................... 18 table 4.1 pin configuration and latch - up conditions ................................ ................................ ................................ ................................ ....... 20 table 5.1 14 - dfn package dimensions ................................ ................................ ................................ ................................ ........................... 22
zsc31150 datasheet ? 2016 integrated device technology, inc . 5 december 6, 2016 1. electrical characteristics 1.1 absolute maximum ratings the absolute maximum ratings are stress ratings only. the zsc31150 might not function or be operable above the recommended op erating conditions. stresses exceeding the absolute maximum ratings m ight also damage the device. in addition, extended exposure to stresses above the recommended operating conditions might affect device reliability. idt does not recommend designing to the absolute maximum ratings. parameters apply in operation temperatur e range and without time limitations. table 1 . 1 absolute maximum ratings no. parameter symbol conditions min max unit 1.1.1 supply v oltage [a] vdde to vsse . - 33 33 vdc 1.1.2 potential at the aout pin [a] v out rela tive to vsse . - 33 33 vdc 1.1.3 analog s upply v oltage [a] vdda rel ative to vssa. vdde - vdda < 0.3 5 v - 0.3 6.5 vdc 1.1.4 voltage at all analog and digital io p ins v a_io v d_io relative to vssa . - 0.3 vdda + 0.3 vdc 1.1.5 storage temperature t stg - 55 150 ? c [a] refer to the zsc31150 technical note C high voltage protection for specification and detailed conditions for high voltage protecti on . 1.2 operating conditions all voltages are related to vssa. see important table notes at the end of the table. table 1 . 2 operating conditions no. parameter symbol conditions min typ max unit 1.2.1 tqe ambient te mperature range for part numbers zsc31150x e x x [a] t amb_tqe tqe - 40 150 ? c tqa ambient temperature range for part numbers zsc31150x a x x [b] t amb_tqa tqa - 40 125 ? c tqi ambient temperature range for advanced performanc e [b] t amb_tqi tqi - 25 85 ? c 1.2.2 supply v oltage vdde 4.5 5.0 5.5 vdc 1.2.3 bridge r esistance bridge voltage mod e [b] , [c] r br_v 2 25 k ? 1.2.4 bridge r esistance bridge current excitation mod e [b] , [c] r br_c see specification 1.2.6 for i br_max 10 k ? 1.2.5 current r eference r esisto r [b] , [d] r ibr i br = vdda / (16 * r ibr ) 0.07 * r br k ? 1.2.6 maximum b ridge c urrent i br_max 2 ma
zsc31150 datasheet ? 2016 integrated device technology, inc . 6 december 6, 2016 no. parameter symbol conditions min typ max unit 1.2.7 maximum b ridge t op v oltage v br_top ( 15 / 16 * vdda ) - 0.3 v 1.2.8 tc c urrent r eference r esisto r [b] tc r ibr behavior influences current generated 50 ppm/k [a] r efer to the temperature profile description i n the zsc31150 technical note C die and package specifications for opera tion in temperature range > 125 c. [b] no measurement in mass production; parameter is guaranteed by design and/or quality observation. [c] symmetric behavior and identical electrical properti es (especially with regard to the low pass characteristic) of both sensor inputs of the zsc31150 are required. unsymmetrical conditions of the sensor and/or external components connected to the sensor input pins o f zsc31150 can generate a failure in signal operation. [d] see application circuit components in table 3 . 1 . 1.3 electrical parameters all parameter values are valid for operating conditions specified in section 1.2 exc ept as noted . all v oltages related to vssa. see important table notes at the end of the table. table 1 . 3 electrical parameters no. parameter symbol conditions min typ max unit 1.3.1 supply current and system operat ion conditions 1.3.1.1 supply current i s without bridge and load current; t amb_ tqa ; f clk ? 3 mhz 5.5 ma 1.3.1.2 clock frequency [a] f osc guaranteed adjustment range (see the zsc31150 functional description for details); t amb_tqa 2 3 4 mhz 1.3.2 analog front - end (afe) characteristics 1.3.2.1 input s pan v in_sp analog gain: 420 to 2.8 1 275 mv/v 1.3.2.2 analog o ffset c ompensation r ange depends on gain adjust ; refer to section 2.3.1 - 300 300 % v in_sp 1.3.2.3 parasitic differential input offset current [a] i in_off within t amb _tqe - 10 10 na within t amb_tqi - 2 2 na 1.3.2.4 common mode input range v in_cm depends on gain adjust ment; no xzc ; see section 2.3.1 0.29 * vdda 0.65 * vdda v 1.3.3 temperature measurement [b] 1.3.3.1 external temperature diode channel gain a tsed 300 1300 ppm fs / (mv/v) 1.3.3.2 external temperature diode bias cu rrent i tse 6 10 20 ? a
zsc31150 datasheet ? 2016 integrated device technology, inc . 7 december 6, 2016 no. parameter symbol conditions min typ max unit 1.3.3.3 external temperature diode input range [a] 0 1.5 v 1.3.3.4 external temperature resistor channel gain a tser 1200 3500 ppm fs / (mv/v) 1.3.3.5 external temperature resistor / input voltage range [a] v tser 0 600 mv/v 1.3.3.6 internal temperature diode sensitivity st tsi r aw values C 1.3.4 analog - to - digital conversion (adc) 1.3.4.1 adc r esolution [a] r adc 13 16 bit 1.3.4.2 adc differential n onlinearity (dnl) [a] dnl adc r adc =13 - b it ; f clk =3mhz ; best fit, 2nd order; complete afe; with adc input range specified in 1.3.4.5 0.95 lsb 1.3.4.3 adc integral n onlinearity (inl) within tqa [a] inl adc 4 lsb 1.3.4.4 adc inl within tqe inl adc 5 lsb 1.3.4.5 adc i nput r ange range 10 90 %vdda 1.3.5 sensor connection check 1.3.5.1 sens or conn ection loss detection threshold r scc_min 100 k ? 1.3.5.2 sensor input short check r ssc_short s hort detection guaranteed 0 50 ? 1.3.5.3 sensor input no - short threshold r ssc_pass a short is not indicated above this threshold 1000 ? 1.3.6 digital - to - analog conversion ( dac ) and analog output (aout pin ) 1.3.6.1 dac r esolution r dac a nalog output, 10 - 90% 12 bit 1.3.6.2 output current sink and source for vdde=5v i src/sink_out v out : 5 - 95%, r load ? out : 10 - 90%, r load ? 1.3.6.3 short circuit current i out_max t o vss e or vdde [c] - 25 25 ma 1.3.6.4 addressable output signal range v sr_out95 @ r load ? ? sr_out90 @ r load ? ? 1.3.6.5 output slew rate [a] sr o ut c load < 50nf 0.1 v/s 1.3.6.6 output resistance in diagnostic mode r out_dia diagnostic range: <4|96>%, r load ? ? load ? ? ? 1.3.6.7 load capacitance [a] c load c3 ( see section 3 ) 150 nf 1.3.6.8 dnl (dac) dnl out - 1.5 1.5 lsb 1.3.6.9 inl tqa (dac) [a] inl out b est fit, r dac =12 - b it - 5 5 lsb
zsc31150 datasheet ? 2016 integrated device technology, inc . 8 december 6, 2016 no. parameter symbol conditions min typ max unit 1.3.6.10 inl tqe (dac) inl out b est fit, r dac =12 - b it - 8 8 lsb 1.3.6.11 output l eak current @150 c i leak_out power or ground loss - 25 25 a 1.3.7 system response 1.3.7.1 startup time [d] t sta t o 1 st output; f clk =3mhz; no rom check; adc 14 - bit and 2nd order 5 ms 1.3.7.2 response time (100% jump ) [a] t resp f clk =4mhz ; 13 - b it, 2nd order ; refer to table 2 . 3 256 512 s 1.3.7.3 bandwidth [a] c omparable to analog sscs 5 khz 1.3.7.4 analog o utput n oise p eak - t o - p eak [a] v noise,pp s horted inputs; bandwidth ? 1.3.7.5 analog o utput n oise rms [a] v noise,rms s horted inputs ; bandwidth ? 1.3.7.6 ratiometricity e rr or re out_5 m aximum error of vdde=5v to 4.5/5.5v 1000 ppm 1.3.7.7 overall failure (deviation from ideal line including the inl, gain, offset and temp erature errors) [e] f all tqi 13 - b it , 2 nd order adc; f clk ? all tqa 0.5 (0.25) % fs f all tqe 1.0 (0.5) % fs [a] no measurement in mass production ; parameter is guaranteed by design and/or quality observation. [b] re fer to section 2.4 . [c] minimum output voltage to vdde or maximum output voltage to vsse. [d] depends on resolution and configuration - start routine begins approximately 0.8ms after power on. [e] xzc is active: additional overall failure of 25ppm/k for xzc=31 at maximum; failure decreases linearly for xzc adjustments lower than 31. 1.4 interface characteristics and eeprom table 1 . 4 interface and eeprom characteristics no. paramet er symbol conditions min typ max unit 1.4.1 i 2 c interface [a] 1.4.1.1 input - high l evel [b] v i 2 c_in_h 0.8 vdda 1.4.1.2 input - low l evel [b] , v i 2 c_in_l 0.2 vdda 1.4.1.3 output - low l evel [b] v i 2 c_out_l open drain, i ol <2ma 0.15 vdda 1.4.1.4 sda load capacitance [b] c sda 400 pf
zsc31150 datasheet ? 2016 integrated device technology, inc . 9 december 6, 2016 no. paramet er symbol conditions min typ max unit 1. 4.1.5 scl clock frequency [b] f scl 400 khz 1.4.1.6 internal pull - up resistor [b] r i 2 c 25 100 k ? 1.4.2 zacwire? one wire interface (owi) 1.4.2.1 input - low l evel [b] v owi_in_l 0.2 vdda 1.4.2.2 input - high l evel [b] v owi_in_h 0.75 vdda 1.4.2.3 pull - up resistance master r owi_pup 0.3 3.3 k ? 1.4.2.4 owi load c apacitance c owi _ load summarized owi line load 50 nf 1.4.2. 5 start w indow [b] t yp: @ f clk =3mhz 96 175 455 ms 1.4.3 eeprom 1.4.3.1 ambient temperature eeprom programming [b] t amb_eep - 40 150 ? 1.4.3.2 write cycles [b] n wri_eep w rite temperature: <=85c 100k w rite temperature: up to 150c 100 1.4.3.3 read cycles [b] , [c] n read_eep read temperature: <=175c 8 * 10 8 1.4.3.4 data retention [b] , [d] t ret_eep 1300h at 175c =100000h at 55c ; 27000h at 125c ; 3000h at 150c) 15 y ea rs 1.4.3.5 programming time [b] t wri_eep p er written word, f clk =3mhz 12 ms [a] r efer to the zsc31150 functional description for timing de tails. [b] no measurement in mass production ; parameter is guaranteed by design and/or quality observation. [c] n ote that the package and temperature version s cause additional restrictions. [d] over lifetime; use calculation she et ssc temperature profile calculation spreadsheet for temperature stress calcul ation; note additional restrictions are caused by different package and temperature versions.
zsc31150 datasheet ? 2016 integrated device technology, inc . 10 december 6, 2016 2. circuit description note: this data sheet provides specifications and a general overview of zsc31150 operation. for details of operation, includi ng configuratio n settings and related eeprom registers, refer to the zsc31150 functional description . 2.1 signal flow the zsc31150 s signal path includes both analog (shown in blue in figure 2 . 1 ) and digital ( pink ) sections. the ana log path is differential; i.e., the differential bridge sensor signal is handled internally via two signal lines that are symmetrical around a common mode po tential (analog ground = vdda/2), which improves noise rejection. consequently, it is possible to amplify positive and negative input signals, which are located within the common mode range of the signal input. figure 2 . 1 block diagram of the zsc31150 the differential signal f rom the bridge sensor is pre - amplified by the programmable gain amplifier (pga). the m ultiplexer (mux) transmits the signals from either the bridge sensor, the external diode, or the separate temperature sensor to the analog - to - digital converter (adc) in a specific sequence (the internal pn - junction (ts) can be used instead of the external temperature diode). next , the adc converts these signals into digital values. the digital signal correction takes place in the calibration microcontroller (cmc). it is ba sed on a correction formula located in the rom and sensor - specific coefficients stored in the eeprom during calibration. depend ing on the programmed output configuration, the corrected sensor signal is output as an analog value or in a digital format ( i 2 c or zacwire ? ). the configuration data and the correction parameters can be programmed into the eeprom via the digital interfaces. 2.2 application modes for each application, a configuration set must be established (generally prior to calibration) by programmin g the on - chip eeprom regarding to the following modes: sensor channel ? sensor m ode: r atiometric bridge excitation in voltage or current supply mode. ? input r ange: t he gain adjustment of the afe with respect to the maximum sensor signal span and the zero poin t of the adc have to be chosen. ? an additional analog offset compensation, the extended zero - point compensation (xzc), must be enabled if required; e.g., if the sensor offset voltage is close to or larger than the sensor span. ? resolution/ r esponse t ime: the adc must be configured for resolution and conversion settings (1 st or 2 nd order). these settings influence the sampling rate, signal integration time, and, as a result, the noise immunity. temperature ? temperature m easurement: t he source for the temperatur e correction must be chosen. p g a t s a d c c m c r o m r a m e e p r o m d a c b a m p z a c w i r e ? i 2 c m u x a n a l o g b l o c k d i g i t a l b l o c k z s c 3 1 1 5 0 d i g i t a l d a t a i / o a n a l o g o u t
zsc31150 datasheet ? 2016 integrated device technology, inc . 11 december 6, 2016 2.3 analog front end (afe) the analog front end (afe) consists of the programmable gain amplifier ( pga), the multi plexer (mux), and the analog - to - digital converter (adc). 2.3.1 programmable gain amplifier (pga) table 2 . 1 shows the adjustable gains, the sensor signal spans, and the allowed common mode range. table 2 . 1 adjustable gains, resulting sensor signal spans , and common mode ranges no. overall g ain a in max. span v in_sp [mv/v] [a ] gain amp1 gain amp2 gain amp3 input common mode range v in_cm as % of vdda [b] xzc = off xzc = on 1 420 1.8 30 7 2 29 to 65 45 to 55 2 280 2.7 30 4.66 2 29 to 65 45 to 55 3 210 3.6 15 7 2 29 to 65 45 to 55 4 140 5.4 15 4.66 2 29 to 65 45 to 55 5 105 7.1 7.5 7 2 29 to 65 45 to 55 6 70 10.7 7.5 4.66 2 29 to 65 45 to 55 7 52.5 14.3 3.75 7 2 29 to 65 45 to 55 8 35 21.4 3.75 4.66 2 29 to 65 45 to 55 9 26.3 28.5 3.75 3.5 2 29 to 65 45 to 55 10 14 53.75 1 7 2 29 to 65 45 to 55 11 9.3 80 1 4.66 2 29 to 65 45 to 55 12 7 107 1 3.5 2 29 to 65 45 to 55 13 2.8 267 1 1.4 2 32 to 57 not applicable [a] recommended internal signal rang e maximum is 80% of the vdda voltage. span is calculated by the following formula: span = 80% / gain. [b] bridge in voltage mode with maximum input signal (with xzc = +300% offset), 14 - bit accuracy. refer to the zsc31150 functional description for usable inpu t signal/common mode range at bridge in current mode. see section 2.3.2 for an explanation of the extended analog zero compensation (xzc). 2.3.2 offset compensation the zsc31150 supports two methods of sensor offset compensation (zero shift): ? digital offset correction ? xzc : a nalog compensation for large offset values (up to a maximum of approximately 300% of the span, depending on the gain adjustment) the d igital sensor offset correction will be processed during the d igital signal correction/conditioning by the calibration microcontroller (cmc). analog sensor offset pre - compensation is needed for compensation of large offset values, which would overdrive the analog signal path by uncompensated gaining. for analog sens or offset pre - compensation, a compensation voltage is added in the analog pre - gaining signal path (coarse offset removal). the analog offset compensation in the afe can be adjusted by 6 eeprom bits (refer to the zsc31150 functional description for details) .
zsc31150 datasheet ? 2016 integrated device technology, inc . 12 december 6, 2016 table 2 . 2 analog zero point shift ranges (xzc) pga gain a in max. span v in_sp [mv/v] offset shift per step as % of full span approximate maximum offset shift [mv/v] approx imate maximum shift [% v in_sp ] ( at 31) 420 1.8 12.5% 7.8 3 88 % 280 2.7 7.6% 7.1 237 % 210 3.6 12.5% 15.5 388 % 140 5.4 7.6% 14.2 237% 105 7.1 12. 5 % 31 388% 70 10.7 7.6% 28 237% 52.5 14.3 12 . 5 % 32 388% 35 21.4 7.6% 57 237% 26.3 28.5 5.2% 52 161% 14 53.75 12.5% 194 388% 9.3 80 7.6% 18 9 237% 7 107 5.2% 161 161% 2.8 267 0.83% 72 26 % 2.3.3 measurement cycle the complete measurement cycle is controlled by the cmc. depending on eeprom settings, the multiplexer (mux) selects the following input signals in a defined sequence: ? temperature measur ed by external diode or thermistor, internal pn - junction , or bridge ? internal offset of the input channel (v off ) ? pre - amplified bridge sensor signal the cycle diagram in figure 2 . 2 shows the basic structure of the m easurement cycle. the bridge sensor measurement count can be configured in e eprom for a value within n=<1,31>. after power - on, the startup routine is processed, which performs all measurements needed to acqui re an initial valid conditioned sensor output. a fter the startup routine, the normal measurement cycle runs. note : the cmv , ssc/scc+ and ssc/scc - measurements are always performed in every cycle independent of the eeprom configuration.
zsc31150 datasheet ? 2016 integrated device technology, inc . 13 december 6, 2016 figure 2 . 2 m easurement cycle start routine 1 temperature auto - zero ? n bridge sensor measurement ? 1 temperature measurement ? n bridge sensor measurement ? 1 bridge sensor auto - zero ? n bridge sensor measurement ? 1 cmv ? n bridge sensor measurement ? 1 ssc/scc+ ? n bridge sensor measurement ? 1 ssc/scc - ? n bridge sensor measurement 2.3.4 analog - to - digital converter the adc is an integrating analog - to - digital c onverter in full differential switched capacitor technique. programmable adc resolutions are r adc =<13, 14> or with segmentation , r adc = <15, 16> bit. the adc can be used as a first or second order converter. in the first order mode , it is inher ently monotone and insensitive to short and long - term instability of the clock frequency. the conversi on cycle time depends on the desired resolution and can be roughly calculated by the following equation where r adc is the adc resolution and t adc_1 is the conversion cycle time in seconds in first - order mode : in the second order mod e , two conversions are stacked with the advantage of a much shorter conversion cycle time but the drawback of a lower noise immunity caused by the shorter signal integration period. the approximate conversion cycle time t adc_2 in second - order mode is calcu lated by the following equation: the calculation formulas for t adc give an overview of conversion time for one ad conversion. refer to the zsc31150 bandwidth calculation spreadsheet for detailed calculation s for sampling time and ba ndwidth. ? ? ? ? ? ? ? 2 2 t adc_1 osc r f adc ? ? ? ? ? ? ? ? 2 2 t 2 / ) 3 ( adc_2 osc r f adc
zsc31150 datasheet ? 2016 integrated device technology, inc . 14 december 6, 2016 the result of the ad conversion is a relative counter result corresponding to the following equation (see the zsc31150 functional description for more detailed equations) : z adc n umber of counts (result of the conversion) r adc selected adc resolution in bit s v adc_diff differential input voltage of the adc v adc _ref r eference voltage of the adc rs adc d igital adc range sh ift (rs adc = 1 / 16 , 1 / 8 , 1 / 4 , 1 / 2 , controlled by the eeprom setting ) the sensor input signal can be shift ed to the optimal input range of the adc with the rs adc value . table 2 . 3 analog output r esolution versus s ample r at e adc adjustment approximated output resolution [a] sample rate f con [ b] averaged bandwidth at f clk adc order r adc digital analog f clk =3mhz f clk =4mhz f clk =3mhz f clk =4mhz [bit] [bit] [bit] [hz] [hz] [hz] [hz] 1 13 13 12 345 460 130 172 14 14 12 178 237 6 7 89 15 14 12 90 120 34 45 16 14 12 45 61 17 23 2 13 13 12 5859 7813 2203 2937 14 14 12 3906 5208 1469 1958 15 14 12 2930 3906 1101 1468 16 14 12 1953 2604 734 979 [a] the adc resolution should be one bit higher th an the required output resolution if the afe gain is adjusted so that more than 50% of the input range is used . otherwise the adc resolution should be more than one bit higher than the required output resolution. [b] the sampling rate (a / d conversion time) is only a part of the whole cycle ; re fer to the zsc31150 bandwidth calculation s preads heet for detailed information . note: the adc s reference voltage adc vref is defined by the potential between and (or to , if selected in eeprom by the bit cfgapp:bref=1). theore tically, the input range adc range_inp of the adc is equivalent to the adc s reference voltage. in practice , the maximum adc input range used should be from 10% to 90% of adc range_inp , which is a necessary condition for ensuring the specified accuracy, stab ility , and nonlinearity parameters of the afe. this condition is also valid for whole temperature range and all applicable sensor tolerances. the zsc31150 does not have an internal failsafe function that verifies that the input meets this condition . ? ? ? ? ? ? ? ? ? ? adc adc_ref adc_diff r adc rs v v 2 z adc
zsc31150 datasheet ? 2016 integrated device technology, inc . 15 december 6, 2016 2.4 temper ature measurement the zsc31150 supports four different methods for acquiring the t emperature data needed for calibration of the sensor signal in the specified temperature range. temperature data can be acquired using one of these temperature sensors: ? an i nternal pn - junction temperature sensor ? an external pn - junction temperature sensor connected to sensor top potential (v brtop ) ? an external resistive half bridge temperature senso r ? the temperature coefficient of the sensor brid ge at bridge current excitation refer to the zsc31150 functional description for a detailed explanation of temperature sensor adaptation and adjustment. 2.5 system control and conditioning calculation the system control supports the following tasks/features: ? c ontro l l ing the measurement cycl e according to the eeprom - stored configuration data ? performing the16 - bit correction calculation for each meas urement signal using the eeprom - stored calibration coefficients and rom - based algorithms ; i.e., the signal conditioning ? managing the start - up seque nce and start ing signal conditioning ? h andl ing communication requests received by the digital interface ? managing failsafe tasks for the functions of the zsc31150 and indicating detected errors with diagnostic states refer to the zsc31150 functional descript ion for a detailed description. 2.5.1 operation modes the internal state machine has three main states: ? t he continuous ly running signal conditioning mode , which is called normal operation mode ( nom ) ? the calibration mode with access to all internal registers and states , which is called command mode ( cm ) ? the failure messaging mode , which is called diagnostic mode ( dm ) 2.5.2 start up phase the start - up phase * consists of following segments : 1. i nternal supply voltage settling phase ( i.e., the vdda - vssa potential ) , which i s ended when the reset signal is disabled through the power - on clear block (po r ). refer to the zsc31150 t echnical n ote C high voltage protection document , section 4 for power on/off thresholds. time (f rom beginning with vdda - vssa=0v): 500 s to 2000 s ; aout is in tri - state 2. s ystem start, eeprom read out , and signature check (and rom check if selected by setting eeprom bit cfgapp:chkrom=1). time : ~200 s (~9000 s with rom - check ; i.e., 28180 clocks ) ; aout is low (dm) 3. p rocessing the start routine for signal cond itioning (all measure ments and conditioning calculation s ). time: 5 x a / d conversion time ; aout behavior depend s on selected owi mode ( refer to section 2.6 ): ? owiana & owidis => aout is low (dm) ? owiwin & owiena => aout is in tri - state * all timings described are roughly estima ted values and are affected by the internal clock frequency. timings are estimated for f clk =3mhz .
zsc31150 datasheet ? 2016 integrated device technology, inc . 16 december 6, 2016 the analog output aout will b e activated at the end of the start - up phase depending on the adjusted output and communication mode ( refer to section 2.6 ). if errors are detected , the diagnos tic mode (dm) is activated and the diagnostic output signal is driven at the output. after the start - up phase , the continuous ly running measurement and calibration cycle is started. refer to zsc31150 bandwidth calculation s preadsheet for detailed informati on about output update rate. 2.5.3 conditioning calculation the digitalized value for the bridge sensor measurement (acquired raw data) is processed with the correction formula to remove offset and temperature d ependency and to compensate non linearity up to 3rd order. the result of the correction calculation is a non - negative 15 - b it value for the bridge sensor in the range [0; 1). this value p is clipped with programmed limitation coefficients and continuously written to the output register of the digital serial interface and the output dac. note: the co nditioning includes up to third - order nonlinearity sensor input correction. the available adjustment ranges depend on the specific calibration parameters ; for a detailed description , refer to zsc31150 functional de scription . basically, o ffset compensation and linear correction are only limited by the lo ss of resolution they will cause . the second - order correction is possible up to approximately 30% of the full scale difference from a straight line ; third order is po ssible up to approximately 20% (adc resolution = 13 - bit). the calibration principle used is able to reduce existing nonlinearity errors of the sensor up to 90%. the temperature calibration includes first and second order correction and should be fairly suf ficient in all relevant cases. adc resolution also influences calibration possibilities ; e.g., 1 additional bit of resolution reduces the calibration range by approximately 50%. the maximum calculation input data width is 14 - bit. the 15 or 16 bit adc resol ution mode uses only a 14 - bit segment of the adc range. 2.6 analog output aout the analog output is used for outputting the analog signal conditioning result and for end of l ine communication via the zacwire tm in terface one - wire communication interface ( owi) . the zsc31150 supports four different modes of the analog output in combination with the owi behavior: ? owiena: a nalog output is deactivated ; owi communication is enabled . ? owidis: a nalog output is active (~2ms aft er power - on) ; owi communication is disabled . ? owiwin: a nalog output will be activated after the time window ; owi communication is enabled in a time window of ~500ms ( maximum ) ; transmission of the start_cm command must be finished during the time window . ? owiana: a nalog output will be activated aft er a ~2ms power on time ; owi communication is enabled in a time window of ~500m s (maximum) ; transmission of the start_cm command must be finished during time window ; to communicate , the internal driven potential at aout must be overwritten by the externa l communication master (aout drive capability is current limited) . the analog output potential is driven by a unity gain output buffer for which the input signal is generated by a 12.4 - bit resistor - string dac. the output buffer (bamp) , which is a rail - to - r ail op amp, is offset compensated and current limited. therefore, a short - circuit of the analog output to ground or the power supply does not damage the zsc31150 . 2.7 serial digital interface the zsc31150 includes a serial digital interface (sif), which is use d for communication with the circuit to calibrate the sensor module. the serial interface is able to communicate with two communication protocols : i 2 c and the zacwire ? one - wire communication interface ( owi). the owi can be used to for an end of lin e cali bration via the analog output aout of the complete assembled sensor module. refer to the zsc31150 functional description for a detailed description of the serial interfaces and communication protocols.
zsc31150 datasheet ? 2016 integrated device technology, inc . 17 december 6, 2016 2.8 failsafe features, watchdog and error detection the zs c31150 detects various possible errors. a detected error is indicated by a change in the internal status in d iagnostic m ode (dm). in this case , the analog output is set to low (minimum possible output value ; i.e., the lower diagnostic range ldr) and the ou tput registers of the digital serial interface are set to a significant error code. a watchdog oversees the continuous operation of the cmc and the running measurement loop. the operation of the internal clock oscillator is verified continuously by the osc illator fail ure detection. a check of the sensor bridge for broken wires is done continuously by two comparators watching the input voltage of each input (sensor connection and short check). additionally , the common mode voltage s of the sensor and sensor i nput short are watched continuously (sensor aging). different functions and blocks in the digital section, e.g. the ram, rom, eeprom , and register content, are watched continuously. refer to the zsc31150 functional description for a detailed description of safety features and methods of error indication . 2.9 high voltage, reverse polarity , and short circuit protection the zsc31150 is designed for 5v power supply operation. the zsc31150 and the connected sensor are protected from overvoltage and reverse polarity damage by an internal supply voltage limiter. the analog output aout can be connected with all potentials (short circuit, over - voltage, and reverse voltage) in the protection range under all potential conditions at the vdde and vsse pins . all external com ponents (see section 3 ) are required to guarantee this operation . t he protection is no t time limited. refer the zsc31150 technical note C high voltage protection for a detailed description of protection cases an d conditions.
zsc31150 datasheet ? 2016 integrated device technology, inc . 18 december 6, 2016 3. application circuit examples the application circuits contain external components that are needed for over - voltage, reverse polarity, and short circuit protection. recommendation : check the zsc31150 product page www.idt.com/zsc31150 for other ap plication examples given in application notes . note: some application notes require a customer login see section 9 for details . table 3 . 1 application circuit parameters symbol parameter min typ max unit notes c1 c 100 470 nf c2 c 100 nf c3 [a ] c 4 47 160 nf the value of c3 is the sum of the load capacitor and the cabl e capacitance . c4, c5 [a ] c 0 10 nf recom mended to increase emc immunity . r1 10 k? r ibr r refer to section 1.2 . ? [a] higher values for c3, c4 , and c5 increase emc immunity. figure 3 . 1 bridge in voltage mode, external diode temperature senso r 2 1 3 4 6 5 7 1 4 1 3 1 2 1 1 1 0 s e r i a l i n t e r f a c e s e n s o r b r i d g e s d a s c l o u t / o w i g n d v s u p p c 3 4 7 n f + 4 . 5 v t o + 5 . 5 v z s c 3 1 1 5 0 v d d a v s s a s d a s c l n . c . v d d v d d e i r t e m p v b r _ t v b p v b r _ b v b n a o u t v s s e 9 8 c 2 1 0 0 n f c 1 1 0 0 n f t e m p e r a t u r e s e n s o r c 5 c 4
zsc31150 datasheet ? 2016 integrated device technology, inc . 19 december 6, 2016 figure 3 . 2 bridge in voltage mode, external thermistor figure 3 . 3 bridge in current mode, temperatur e measurement via bridge tc 2 1 3 4 6 5 7 1 1 1 3 1 2 1 0 9 8 s e r i a l i n t e r f a c e s e n s o r b r i d g e s d a s c l o u t / o w i g n d v s u p p c 3 4 7 n f + 4 . 5 v t o + 5 . 5 v z s c 3 1 1 5 0 v d d a v s s a s d a s c l n . c . v d d v d d e i r t e m p v b r _ t v b p v b r _ b v b n a o u t v s s e c 2 1 0 0 n f c 1 1 0 0 n f t e m p e r a t u r e s e n s o r c 5 r 1 p t 1 0 0 0 c 4 1 4 2 1 3 4 6 5 7 8 1 4 1 3 1 1 1 2 1 0 9 s e r i a l i n t e r f a c e s e n s o r b r i d g e s d a s c l o u t / o w i g n d v s u p p c 3 4 7 n f + 4 . 5 v t o + 5 . 5 v z s c 3 1 1 5 0 v d d a v s s a s d a s c l n . c . v d d v d d e i r t e m p v b r _ t v b p v b r _ b v b n a o u t v s s e c 2 1 0 0 n f c 1 1 0 0 n f c 4 * r i b r * c 4 a n d c 5 m u s t b e c o n n e c t e d t o v b r _ b w h e n u s i n g c u r r e n t m o d e b e c a u s e v b r _ b a n d v s s a a r e n o t s h o r t e d i n t h i s c a s e . c 5 *
zsc31150 datasheet ? 2016 integrated device technology, inc . 20 december 6, 2016 4. pin configuration, latch - up and esd protection 4.1 pin configuration and latch - up conditions table 4 . 1 pin configuration and latch - up conditions pin name d escription notes usage/ connection [a] latch - up related application circuit restrictions and/or notes 1 vdda positive analog supply voltage analog io required/ - 2 vssa negative analog supply voltage analog io required/ - 3 sda i 2 c data io digital io, pull - up - /vdda trigger current/voltage to vdda/vssa: +/ - 100ma or 8/ - 4v 4 scl i 2 c clock digital in, pull - up - /vdda 5 n.c. no connection 6 vdd positive digital supply voltage analog io required or open/ - o nl y capacitor to vssa is allowed, otherwise no application access 7 vdde positive external supply voltage supply required/ - trigger current/voltage: - 100ma/33v 8 vsse negative external supply voltage ground required/ - 9 aout analog output and one wire i f io io required/ - trigger current/voltage: - 100ma/33v 10 vbn negative input sensor bridge analog in required/ - 11 vbr_b bridge bottom potential analog io required/vssa depending on application circuit, short to vdda/vssa possible 12 vbp positive input sensor bridge analog in required/ - 13 vbr_t bridge top potential analog io required / vdda 14 irtemp temp sensor and current source resistor analog io - / vdda, vssa depending on application circuit [a] usage : if required is specified, an electrical co nnection is necessary ; refer to the application circuits in section 3 . connection: to be connected to this potential if not used or if no application/configuration - r elated constraints are given. 4.2 esd protection all pins have an esd p rotection of > 2000v. additionally , the pins vdde, vsse and aout have an esd p rotection of >4000v. esd p rotection refer enced to the h uman b ody m odel is tested with devices during product qualification. the esd test follows the human body model with 1.5k ? /100pf based on mil 883, method 3015.7.
zsc31150 datasheet ? 2016 integrated device technology, inc . 21 december 6, 2016 5. package 5.1 ssop14 package the standard package s of the zsc31150 are the ssop14 green package (5.3mm body w idth) with a lead pitch of 0.65 mm and the dfn14 ( 4 mm x5mm ) package with a lead pitch of 0.5mm . for the ssop14 pa ckage markings shown in figure 5 . 1 , yyww refers to the last two digits of the year (yy) and two digits for the work - week designation (ww). xxxxxxxx refers to the lot number. figure 5 . 1 ssop14 pin diagram 5.2 14 - dfnpackage for the 14 - dfn package , the pin assignment is the same as in ssop14 . refer to the zsc31150 technical note C die and package specifications for a description of package marking s. figure 5 . 2 provides the dimensions for the 14 - dfn package option, which are based on jedec mo - 229. the 14 - dfn package has wettable flanks. v d d e v d d n . c . s c l s d a v s s a v d d a v s s e a o u t v b n v b r _ b v b p v b r _ t i r t e m p 1 4 1 z s c 3 1 1 5 0 g e g 1 x x x x x x x x y y w w
zsc31150 datasheet ? 2016 integrated device technology, inc . 22 december 6, 2016 figure 5 . 2 outline drawi ng for 14 - dfn package with wettable flanks table 5 . 1 14 - dfn package dimensions dimension minimum maximum a 0.8 0.9 a 1 0 0.05 b 0.2 0.3 e 0.5 nominal h d 3.9 4.1 h e 4.9 5.1 l 0.3 0.5 6. quality and reliability the zsc31150 is qualified according to the aec - q100 standard, operating temperature grade 0. a fit rate < 5fit (temp erature =55c, s=60%) is guaranteed . a typical fit rate of the c7d technology , which is used for zsc31150 , is 2.5fit. 7. customization for high - volume ap plications, which require an upgraded or downgraded functionality compared to the standard zsc31150 , idt can customize the circuit design by adding or removing certain functional blocks. 0 , 0 8 a 1 a b e h d h e l 1 4 8 1 7 1 8 1 4 7 e x p o s e d p a d 4 . 4 x 2 . 5 m m t o p v i e w b o t t o m v i e w
zsc31150 datasheet ? 2016 integrated device technology, inc . 23 december 6, 2016 for this purpose, idt has a considerable library of sensor - dedicated circuitry blocks. as a result, idt can provide a custom solution quickly. please contact idt for further informatio n. 8. ordering information product sales code description package zsc31150geb zsc31150 die temper ature range: - 40c to +150c unsawn on wafer zsc31150gec zsc31150 die temperature range: - 40c to +150c sawn on wafer frame zsc31150ged zsc31150 die temperature range: - 40c to +150c waffle pack zsc31150geg2 - r zsc311 50 14 - dfn (5 ? 4 mm with wetta ble flank temperature range: - 40c to 150c tape & reel zsc31150gag2 - r zsc31150 14 - dfn (5 ? 4 mm with wettable flank temperature range: - 40c to 125c tape & reel zsc31150gab zsc31150 die temperature range: - 40c to +125c unsawn on wafer zsc31150ga c zsc31150 die temperature range: - 40c to +125c sawn on wafer frame zsc31150geg1 zsc31150 ssop14 temperature range: - 40c to +150c tube: add - t to sales code tape & reel: add - r zsc31150glg1 zsc31150 ssop14 temperature range: - 40c to +150c (l ong life: 5000h @150c) tube: add - t to sales code tape & reel: add - r ZSC31150GAG1 zsc31150 ssop14 temperature range: - 40c to +125c tube: add - t to sales code tape & reel: add - r zsc31150kitv1p2 zsc31150 ssc evaluation kit v1.2 : three intercon necting boards, five zsc31150 ssop14 samples, usb cable (software can be downloaded from product page at www.idt.com/zsc31150 ) zsc31150mcsv1p1 modular mass calibration system (msc) v1.1 for zsc31150: mcs boards , cable, connectors (software can be downloaded from product page at www.idt.com/zsc31150 ) 9. related documents and tools visit the zsc31150 product page www.idt.com/zs c31150 on the idt website at www.idt.com or contact your nearest sales office for the latest version of th is document and related document s.
zsc31150 datasheet ? 2016 integrated device technology, inc . 24 december 6, 2016 10. glossary term description adc analog - to - digital converter aec automotive ele ctronics council afe analog front end aout analog output bamp buffer amplifier cm command mode cmc calibration microcontroller cmv common mode voltage cmos complementary metal oxide semiconductor dac digital - to - analog converter dm diagnostic mode eeprom electrically erasable programmable read only memory esd electrostatic device ldr lower diagnostic range mux multiplexer nom normal operation mode owi one wire interface p bridge sensor measurement; e.g., pressure sensor pga programmable gain amplifier poc power on clear ram random - access memory risc reduced instruction set computer rms root - mean - square rom read only memory scc sensor connection check sif serial interfa ce ssc+ positive - biased sensor short check ssc - negative - biased sensor short check ts temperature sensor xzc extended zero compensation
zsc31150 datasheet ? 2016 integrated device technology, inc . 25 december 6, 2016 11. document revision history date description september 20, 2008 (revision 1.01) section 6: fit rate added. section 1 .5.2: rom check time revised/corrected. section 5.3.4.3: sc C no detection limit added . september 20, 2009 (revision 1.02) update to new zmdi template . october 2, 2009 (revision 1.03) update to zmdi denotation . october 22, 2009 (revision 1.04) formattin g and linking issues solved . february 26, 2010 (revision 1.05) update for zmdi template, including zsc31150 functional description at page 2 and 3 . added ordering codes for zsc31150 and evaluation kits. extended glossary. update for contact information. july 29, 2010 (revision 1.06) correct offset shift per step and approx. maximum offset shift in table 2 . 2 for pga gain = 105 and 52.5. moved 1.4.1.6 internal pull - up resistor into section 1.4.1 in table 1 . 2 . redrew of sensor bridge in figure 3 . 1 , figure 3 . 2 , and figure 3 . 3 . added comment for c4 and c5 in figure 3 . 3 . renamed zmd31150 as zsc31150. august 31, 2010 (revision 1.07) connection of r ibr in figure 3 . 3 corrected . august 15, 2011 (revision 1.08) update ord ering informat ion with long life automotive in ordering informatio n on page 3 and section 8 . december 15, 2012 (revision 2.00) update for part numbers and idt contac t information. minor edits. march 31, 2014 (revision 2.10) revision of specifications in section 1.4.2. recommended internal signal range revised to 80%. owi interface parameters list extended. adc formula corrected. dfn14 package added. minor edits for c larity. updated contact information. updated imagery for cover and headings. april 30, 2014 (revision 2.20) added notation that dfn14 package has wettable flanks. update for contact information and addition of cad model files to section 9 . august 27, 2014 (revision 2.30) minor edits on page 2. minor edits for die description in part code tables. december 3, 2014 (revision 2.40) corrected connection of temperature ptc sensor in figure 3 . 2 . update for contact information. july 27, 2015 (revision 2.41) update for order code for zsc31150 ssc evaluation kit order code. update for contact information. january 29, 2016 changed to idt branding. the document release date is no w the revision reference. december 6, 2016 added zsc31150gab and zsc31150gac order codes . correction for order codes for kit and mcs. updates for formatting and minor edits.
zsc31150 datasheet ? 2016 integrated device technology, inc . 26 december 6, 2016 corporate headquarters 6024 silver creek valley road san jose, ca 95138 www.idt.com sales 1 - 800 - 345 - 7015 or 408 - 284 - 8200 fax: 408 - 284 - 2775 www.idt.com/go/sales tech support www.idt.com/go/support disclaimer integrated device technology, inc. (idt) reserves the right to modify the products and/or specifications described herein at any time, without notice, at idt's sole discretion. performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer pro ducts. the information contained herein is provided without representation or warranty of any kind, whether express or implied, in cluding, but not limited to, the suitability of idt's products for any particular purpose, an implied warranty of merchantability, or non - infringement of the intellectual property rights of others. this document is presented only as a guide and does not co nvey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of user s. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the united st ates and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossa ry . all contents of this document are copyright of integrated device technology, inc. all rights reserved.

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